This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-398184, filed Dec. 27, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (Silicon On Insulator) structure in which a semiconductor layer is formed in a partial region of a semiconductor substrate with an insulating film interposed between the semiconductor substrate and the semiconductor layer, or an SON (Silicon On Nothing) structure in which a semiconductor layer is formed in a partial region of a semiconductor substrate with a cavity region interposed between the semiconductor substrate and the semiconductor layer.
2. Description of the Related Art
Recently, a substrate (to be referred to as an SOI substrate hereinafter) having an SOI structure is considered to be promising as a substrate capable of forming an element which can improve the operating speed and reduce the power consumption. This SOI substrate is particularly attracting attention as a substrate for a logic device required to operate at high speed. On the other hand, when a memory element such as a DRAM or an analog circuit such as a power amplifier is formed on the SOI, the element or circuit malfunctions owing to the floating effect. Accordingly, a DRAM or an analog circuit must be formed not on the SOI but on common silicon in order to stabilize the operation of the memory or circuit.
To form both a logic device and a memory device on a substrate, therefore, it is possible to use a partial SOI substrate in which a silicon region not having the SOI structure and an SOI region having the SOI structure are partially formed on a substrate beforehand. It is necessary to form a logic circuit on the SOI region in which a buried oxide film is present below silicon, and to form a DRAM and an analog circuit on the common silicon region in which no buried oxide film is present below silicon.
Unfortunately, analog elements forming the analog circuit are readily influenced by noise, so these elements are preferably electrically disconnected from the logic circuit and the memory circuit. On the partial SOI substrate, the logic circuit is formed on the SOI region and subjected to element isolation. Therefore, this logic circuit and the analog circuit are electrically disconnected. However, the DRAM and the analog circuit formed on the same silicon region are formed adjacent to each other, so noise propagation from the DRAM to the analog circuit is a problem.
Also, when an input/output circuit for exchanging signals with another semiconductor device is formed on the SOI region, high voltages are applied to elements forming this input/output circuit because the SOI region is insulated. This easily brings about electrostatic breakdown. In addition, the side surfaces of a semiconductor layer in the SOI region are covered with SiO2 for element isolation, and the bottom surface of this semiconductor layer is covered with SiO2 of the buried oxide film. Hence, an element formed on the SOI region has the drawback that heat generated from this element when the element is driven is not efficiently dissipated.
Furthermore, with the advancing micropatterning of elements, junctions must be made shallow. When annealing is performed to activate an impurity such as boron (B), phosphorus (P), or arsenic (As) ion-implanted into a semiconductor layer, the impurity diffuses more than necessary if the annealing time is long, and this deepens the junction. To prevent the formation of a deep junction, the semiconductor layer must be heated and cooled rapidly. A halogen lamp or the like is generally used in this heating. However, a difference between the heat absorption efficiencies between the SOI region and the silicon region produces a temperature difference between these regions. This temperature difference may form crystal defects such as slips in the substrate.
A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer formed in a first region of a semiconductor substrate with an insulating film interposed between the semiconductor substrate and the first semiconductor layer, and a plurality of second semiconductor layers formed in second regions of the semiconductor substrate.